In the manufacture of semiconductor integrated circuits, a laminated structure is built by repeating processes of exposing, etching, depositing (plating) and polishing a wafer to form a desired circuit. In the processes, a plurality of semiconductor integrated circuits is formed simultaneously on one wafer to increase productivity.
In particular, in recent years, there has been a demand for increasing the wafer diameter to increase the number of circuits that can be produced at a time. However, as a wafer becomes larger, it is increasingly difficult to process a wafer evenly at the central portion and the peripheral portion thereof. Meanwhile, circuits are more and more miniaturized and high precision processing is asked for.
For example, copper wiring, which prevails in recent years, is formed by electro-chemical plating (ECP) in which wiring grooves are formed on an insulator and the insulator is subjected to copper plating to fill the grooves with copper. Since not only the wiring grooves but also the entire surface of the insulator are covered with the copper plating in this process, chemical mechanical polishing (CMP) is used for polishing to expose a wiring pattern.
If a large height difference is generated on a wafer as a result of the CMP, a height variation in the copper wiring, a short circuit of wiring due to residual copper or the like may be caused. In any case, performance is degraded and yield is decreased.
In the related art, a layout is modified after actually manufacturing the circuits and experiencing an error. This is very inefficient in terms of cost and time cost because a wafer is actually produced. Therefore, a method for simulating the CPM to conduct prediction and modification before manufacture is proposed.
However, if a plurality of materials such as metal for wiring and an insulator is polished, there is a large difference in the polishing rate. Thus, if the density distribution of materials is biased, a phenomenon of overpolishing called an edge over erosion (EOE) occurs. In the EOE, overpolishing abruptly occurs at a rate higher than a polishing rate of a single material.
As an attempt to equalize the density in the related art, dummy wiring is inserted in a layout to thereby equalize the density. However, even if the density is equalized in a semiautomatic manner, the density remains biased. Further, it is unclear whether the EOE is caused by the density bias.
The EOE may occur even the wiring density is within a range defined by a design rule. In addition, if the range of the wiring density is more strictly defined by raising the lower limit, the dummy wiring will be asked for to be inserted more than in the related art. As a result, the configuration will become more complicated and the data size of the layout will increase. Further, since the dummy wiring is provided close to the wiring for actual use, the circuit performance may be degraded due to a change in a signal delay or the like. Accordingly, it is desired to pinpoint and modify a spot where the EOE occurs.
A model of the polishing amount of the EOE is not known, and it is thus difficult to know the occurrence of the EOE in advance by simulating the CMP or the like. However, if it is attempted to equalize the wiring density manually, the workload will be high, and the data size for the layout will be increased because the dummy wiring is arranged irregularly in the layout.
Therefore, it has been an important issue to realize a technique for efficiently designing a layout that suppresses occurrence of the EOE.